About the role :
If you’re creative and autonomous, we want to hear from you! At NVIDIA, as a senior ASIC engineer you will have the opportunity to shape some of the most incredible products on the market today from products like DGX-1, P100, the Shield to Tesla for Data Centers. Your work will touch every industry – from medical, to auto, to robotics and more.
- As a member in our team, you will work with multi-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
- You will assist in the development test plans and verification infrastructure.
- Help develop and deploy DFT methodologies for our next generation products.
- Innovate methods to reduce test time and improve yield and test quality.
Candidate requirements :
- BSEE or equivalent experience
- 3+ years of experience or MS/PhD in DFT or related domains with relevant experience
- Solid knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
- Experience in development of pre and post silicon test plans and verification infrastructure
- Possess excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
- You will also have good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
- Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
- Strong programming and scripting skills in Perl, Python or Tcl desired
- Exceptional written and oral and interpersonal skills with the curiosity to work on rare challenges